Embedded enclosure for effective electromagnetic radiation reduction

ABSTRACT

In one embodiment of the invention, an embedded enclosure includes a power plane and first and second ground planes. The power plane has a power surface and a power periphery, and couples power to signals of an integrated circuit operating at a fundamental frequency. The first and second ground planes have first and second ground surfaces and first and second ground peripheries, respectively. The first and second ground planes couple ground to the signals. The first and second ground planes are separated from the power plane by first and second distances, respectively. The first and second ground surfaces are larger than the power surface. The first and second ground peripheries extend at least third and fourth distances from the power periphery, respectively. The third and fourth distances are N and M times larger than the first and second distances, respectively.

BACKROUND

1. Field of the Invention

This invention relates to packaging. In particular, the inventionrelates to component packaging.

2. Description of Related Art

High performance integrated circuits are becoming more integrated,smaller and faster. As clock frequencies increase, radiation frompackages and interposers becomes a serious electromagnetic interference(EMI) or electromagnetic compatibility (EMC) problem. In addition, asthe footprint of integrated devices becomes smaller, discrete capacitorsare not effectively attached close to the device because the size ofdiscrete capacitors tend to be large. Even when capacitors are madeintegral to the device, large amount of instantaneously charged ordischarged currents may cause undesirable EMI radiation.

Techniques to reduce EMI radiation have disadvantages. One techniqueuses metal enclosure to cover the entire device or the assemblyincluding the motherboard. This technique is expensive and ineffective.

Therefore, there is a need to have an efficient technique to packageintegrated circuits to reduce electromagnetic radiation.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the present invention will becomeapparent from the following detailed description of the presentinvention in which:

FIG. 1 is a diagram illustrating a packaged device in which oneembodiment of the invention can be practiced.

FIG. 2A is a diagram illustrating an embedded enclosure for organic landgrid array according to one embodiment of the invention.

FIG. 2B is a diagram illustrating an embedded enclosure for flip chippin grid array according to one embodiment of the invention.

FIG. 3A is a diagram illustrating a cross section view for the embeddedenclosure according to one embodiment of the invention.

FIG. 3B is a diagram illustrating a top view for the embedded enclosureaccording to one embodiment of the invention.

FIG. 4 is a diagram illustrating a top view for the embedded enclosurewith EMI contacts according to one embodiment of the invention.

FIG. 5 is a diagram illustrating a top view for the embedded enclosurewith EMI outer ring according to one embodiment of the invention.

FIG. 6 is a diagram illustrating an integral capacitor with embeddedenclosure according to one embodiment of the invention.

FIG. 7 is a diagram illustrating a cross sectional view of the integralcapacitor according to one embodiment of the invention.

DESCRIPTION

In one embodiment of the invention, an embedded enclosure includes apower plane and first and second ground planes. The power plane has apower surface and a power periphery, and couples power to signals of anintegrated circuit operating at a fundamental frequency. The first andsecond ground planes have first and second ground surfaces and first andsecond ground peripheries, respectively. The first and second groundplanes couple ground to the signals. The first and second ground planesare separated from the power plane by first and second distances,respectively. The first and second ground surfaces are larger than thepower surface. The first and second ground peripheries extend at leastthird and fourth distances from the power periphery, respectively. Thethird and fourth distances are N and M times larger than the first andsecond distances, respectively.

In the following description, for purposes of explanation, numerousdetails are set forth in order to provide a thorough understanding ofthe present invention. However, it will be apparent to one skilled inthe art that these specific details are not required in order topractice the present invention. In other instances, well-knownelectrical structures and circuits are shown in block diagram form inorder not to obscure the present invention.

FIG. 1 is a diagram illustrating a packaged device 100 in which oneembodiment of the invention can be practiced. The packaged device 100includes an encapsulant 110, a die 120, an embedded enclosure 140, aplurality of contacts 145, a socket 150, and a printed circuit board(PCB) 160.

The encapsulant 110 encapsulated the die 120 and the embedded enclosure140. The encapsulant 110 may be made by plastic or any appropriatematerial. The die 120 contains an integrated circuit having electroniccircuits and signal traces connecting elements of the electroniccircuits. The integrated circuit may be any type of integrated circuitsuch as a microprocessor, an application specific integrated circuit(ASIC), a programmable logic device (PLD), a digital signal processor(DSP), a gate array, a memory device, a logic device, etc. The die 120has a plurality of controlled collapse chip connection (C4) solderballs, or C4 bumps, 130. The C4 bumps 130 are attached to a plurality ofmetal conductive pads or C4 bump pads (not shown) on the top surface ofthe embedded enclosure 140.

The embedded enclosure 140 provides electromagnetic interference (EMI)shielding for the integrated circuit in the die 120 when operating. Theembedded enclosure 140 is part of the packaged device 100 and can useexisting ground planes, vias, contacts (e.g., C4 bumps, ball grid arrayballs, and pins) without extra cost. The embedded enclosure 140 helpsmeeting regulations and requirements mandated by government agencies orprivate standards organizations.

The plurality of contacts 145 provide contacts to the socket 150. Thecontacts 145 may be pins for a pin grid array (PGA) or solder balls. Thesocket 150 provides placement of the encapsulant 110 onto the PCB 160.The socket 150 have a number of socket legs 170 to make contact with thesignal, ground, and power traces/planes on the PCB 160. The PCB 160 isan assembly having other circuits or packaged devices connectedtogether.

FIG. 2A is a diagram illustrating an embedded enclosure 140 for organicland grid array (OLGA)package according to one embodiment of theinvention. The enclosure 140 includes an OLGApackage enclosure 210 andan interposer 220.

The OLGApackage enclosure 210 is used for OLGA packaging model. TheOLGApackage enclosure 210 has a plurality of solder balls 215. Thesolder balls 215 may be the C4 bumps which are attached to the topsurface of the interposer 220. The interposer 220 provides mounting pinsto allow insertion of the packaged device 100 into apin grid arraysocket on the PCB.

FIG. 2B is a diagram illustrating an embedded enclosure 140 for flipchip pin grid array (FCPGA)package according to one embodiment of theinvention. The enclosure 140 has a contact array which consists of pinsfor the FCPGA and can be used directly to mount on a socket.

FIG. 3A is a diagram illustrating a cross sectional view for theembedded enclosure 140 according to one embodiment of the invention. Theenclosure 140 includes ground planes 310, 340, and 360, a signal plane320, and power planes 330 and 350. The use of three ground planes andtwo power planes is for illustrative purposes only. Any number of groundand power planes can be used.

The ground planes 310, 340, and 360 are approximately of the same size,which is comparable to the size of the die 120 (FIG. 1). The groundplanes 310, 340, and 360 are connected by a connected via chain 370.

The signal plane 320 provides signal traces to the integrated circuit inthe die 120 (FIG. 1) and is located between the power plane 330 and theground plane 310. The signals of the integrated circuit may operate at afundamental frequency. For EMI and EMC considerations, typically thehighest frequency of interest is approximately ten times the fundamentalfrequency. For example, this fundamental frequency may be the corefrequency of the microprocessor. The power plane 330 provides powercoupling to the signals of the integrated circuit in the die 120. Thepower plane 330 has a power surface and a power periphery. Similarly,the ground planes 310, 340 and 360 have respective groundpower surfacesand groundpower peripheries and provide ground coupling for theintegrated circuit of the die 120. To provide proper EMI and/or EMCreduction, the size and distance of the power planes 330 and 350, andthe ground planes 310, 340, and 360 preferably follow a distinctrelationship.

Suppose the distance between a ground plane and a power plane is H. Theground surface of the ground plane is larger than the power surface ofthe power plane. For example, the ground surface 345 of the ground plane340 is larger the power surface 355 of the power plane 350. The minimumdistance between a ground periphery and a power periphery is S. In otherwords, from the top down, the power plane is covered by the ground planeand the distances between the edges of the power plane to the edges ofthe ground plane are equal to or larger than S.

In one embodiment, the distance relationship between S and H is S>20H.This is known as the 20-H rule. This concept is premised on the factthat radio frequency (RF) currents exit on the outer edges of powerplanes due to magnetic flux leakage. The radio frequency currents causefringing of current between power and ground planes, thereby radiatingRF energy into free space. To minimize the fringing effect, the groundplane is larger than the power plane (e.g., 20-H). In alternativeembodiments, S may be less than 20 times H, and may be 10H, 5H, or even1H.

FIG. 3B is a diagram illustrating a top view for the embedded enclosureaccording to one embodiment of the invention. The top view shows theground plane 340 is above the power plane 350.

The ground and power planes 340 and 350 have peripheries 347 and 357,respectively. The distance between the power periphery 357 and groundperiphery 347 is at least S. In other words, the distance between thepower periphery 357 and ground periphery 347 does not have to beuniformly equal to S, but could be equal to or larger than S.Furthermore, although the periphery is shown to be rectangular, anyshape or form can be used, e.g., square, circular, triangular, or evenirregular, as long as the distance relationship is maintained.

The ground plane 340 has the connected via chain 370 which includes anumber of vias located around the first ground periphery 347 and outsidethe power periphery 357. The vias having adjacent vias which are spacedapart by a via distance d. In one embodiment, the via distance d issmaller than a quarter wavelength of the highest frequency of interest.The distance between adjacent vias from one via to another may bedifferent, but the maximum separation between adjacent vias should beless than a quarter wavelength of the highest frequency of interest.

Ideally, sinusoidal signals are perfect in that they only contain energyat one frequency, and no harmonic energy, i.e., energy at multiples ofthe fundamental frequency. However, in reality, signals are notperfectly sinusoidal, and contain some energy at harmonic frequencies.For integrated circuits, the amount of energy radiated at differentharmonic frequencies is typically measured to determine which harmonicfrequencies, if any, have the highest amount of energy radiated. Thefundamental frequency is then multiplied by the value N, where the N-thharmonic has the highest amount of energy radiated. For example, if the10-th harmonic radiates the highest amount of energy, the fundamentalfrequency is multiplied by 10. This value is then converted towavelength, using the following equation:

 c=λ*f  (1)

where c is the speed of light, λ is the wavelength, and f is thefundamental frequency. The spacing d between adjacent vias is then lessthan λ/4, according to the following equation:

d<λ/4=c/(4*N*f)  (2)

For example, if N=10, f=1 GHz, c=3×10⁸ m/s, then:

d<3×10⁸ m/s/(4*10* 1×10⁹ cycles/s)=0.75 cm  (3)

FIG. 4 is a diagram illustrating a top view for the embedded enclosure140 with EMI contacts according to one embodiment of the invention. Theembedded enclosure 140 has the ground plane 340, the power plane 350,and a contact array 410.

The contact array 410 includes a number of contacts 420 made byappropriate contact type depending on the packaging type. For example,the contact array 410 may include an array of C4 bumps, BGA balls (forOLGA packaging), or pins (for FCPGA packaging). These contacts 420 maybe connected to the power plane 350 and/or the ground plane 340. Asshown in FIG. 4, the contacts 420 are shown at random as filled black toindicate that they are connected to the power plane 350 and unfilledwhite to indicate that they are connected to the ground plane 340. Theperiphery of the contact array 410 is approximately the same as theperiphery of the power plane 350.

The ground plane 340 has a plurality of adjacent contacts 420 to provideEMI shielding. The EMI adjacent contacts 420 are spaced apart by acontact distance d that is smaller than a quarter wavelength of thefundamental frequency The calculations are the same as given byequations (1) through (3) above. The adjacent contacts 420 are the sametype with the contacts 420 in the contact array 410. In other words, theadjacent contacts 420 may be controlled collapse chip connection (C4)bumps, ball grid array (BGA) balls, or flip chip pin grid array (FCPGA)pins.

FIG. 5 is a diagram illustrating a top view for the embedded enclosure140 with EMI outer ring according to one embodiment of the invention.

In this embodiment, there are no adjacent contacts outside the peripheryof the power plane 350. Instead, the contact array 410 includes an innerring 510 and an outer ring 520. The inner ring 510 includes contacts 515that are connected to at least the ground plane 340 and the power plane350. The outer ring 520 provides EMI shielding and includes contacts 525of the same type that are attached to the ground plane 340. The contacts515 and 525 may be C4 bumps, BGA balls (for OLGA packaging), or pins(for FCPGA packaging).

FIG. 6 is a diagram illustrating a packaged device 600 using an integralcapacitor with embedded enclosure according to one embodiment of theinvention. The packaged device 600 includes integral capacitors 610 and640, a die 620, and a package substrate 630. The use of two integralcapacitors 610 and 640 are for illustrative purposes only. In oneembodiment, only one integral capacitor can be used. For example, thepackaged device 600 may include either the integral capacitor 610 or theintegral capacitor 640.

To reduce noise caused by high frequency signals and power fluctuations,there should be a number of bypassing capacitors. Using discretecapacitors in a typical circuit may occupy additional space and increasecomponent and assembly costs. The integral capacitors 610 and 640 areintegral to the packaged device 600 and therefore provide an effectivemeans for noise reduction. In addition to providing capacitor bypassing,the integral capacitors 610 and 640 also provide electromagneticradiation reduction. The integral capacitors 610 and 640 are essentiallysimilar. The integral capacitor 610 is attached to the top surface ofthe die 620 by a number of C4 bumps 615 while the integral capacitor 640is attached to the bottom surface of the package substrate 630 by anumber of C4 bumps 645. Since the integral capacitors 610 and 640 aresimilar, a description of the integral capacitor 610 is sufficient.

The die 620 contains an integrated circuit operating at a fundamentalfrequency. The die 620 is essentially similar to the die 120 shown inFIG. 1. The die 620 has a number of C4 bumps 625 attached to metalconductive pads or C4 bump pads (not shown) on the top surface of thepackage substrate 630. The integral capacitors 610 and 640 providecharge storage for the integrated circuit of the die 620.

The package substrate 630 can be formed from a ceramic material ornon-ceramic materials such as FR-4. The package substrate 630 isattached to pads on a printed circuit board (not shown) by a number ofsolder balls 650. The solder balls 650 may be the BGA balls.

The integral capacitors 610 and 640 are constructed using the embeddedenclosure as described above. The integral capacitors 610 and 640essentially form an embedded Faraday cage to reduce electromagneticradiation. The integral capacitors 610 and 640 typically havedimensions, size and shape comparable with the die 620. In oneembodiment, the dimensions are approximately 1.5 cm×1.5 cm. Thecapacitance value depends on the noise reduction requirements. Typicalvalues range from 10 to 50 microfarads (F).

FIG. 7 is a diagram illustrating a cross sectional view of the integralcapacitor 610 according to one embodiment of the invention. The integralcapacitor 610 includes ground planes 710, 730, and 750, power planes 720and 740, dielectric material 715, and via chain 760. The use of threeground planes 710, 730, and 750, and two power planes 720 and 740 arefor illustrative purposes only. In alternative embodiments, the integralcapacitor 610 may include any number of ground and power planes. Forexample, the integral capacitor 610 may include only the ground plane710 and the power plane 720.

The ground planes and the power planes follow the distance relationshipas discussed above. For illustrative purposes, only the distancerelationship between the ground plane 710 and the power plane 720 isdescribed. The distance relationship for the other ground and powerplanes is similar.

The dielectric layer 715 is formed between the ground plane 710 and thepower plane 720. The material of the dielectric layer 715 may be anysuitable material having high dielectric constant k, such as FR-4 orX7-R.

The ground plane 710 has a ground surface and a ground periphery. Thepower plane 720 has a power surface and a power periphery. The groundsurface is larger than the power surface. Suppose the distance betweenthe power periphery and the ground periphery is S and the distancebetween the ground surface and the power surface is H, then the distancerelationship between S and H is S>20H. Like in the embedded enclosure,alternative embodiments may follow the relationship S>10H, S>5H, orS>1H.

The via chain 760 includes a number of adjacent vias which areelectrically connected to the ground plane 710 and electrically isolatedfrom the power plane 720. Similarly to the embedded enclosure shown inFIG. 3B, the adjacent vias are separated by a distance less than onequarter of the wavelength. The calculations of the wavelength followsthe equations (1) through (3).

While this invention has been described with reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. Various modifications of the illustrative embodiments,as well as other embodiments of the invention, which are apparent topersons skilled in the art to which the invention pertains are deemed tolie within the spirit and scope of the invention.

What is claimed is:
 1. An enclosure comprising: a power plane having apower surface and a power periphery, the power plane coupling power tosignals of an integrated circuit operating at a fundamental frequency;and first and second ground planes having first and second groundsurfaces and first and second ground peripheries, the first and secondground planes coupling ground to the signals, the first and secondground planes being separated from the power plane by first and seconddistances, respectively, the first and second ground surfaces beinglarger than the power surface, the first and second ground peripheriesextending at least third and fourth distances from the power periphery,respectively, the third and fourth distances being N and M times largerthan the first and second distances, respectively.
 2. The enclosure ofclaim 1 wherein the first and second ground planes have first and secondpluralities of vias located around the first and second groundperipheries, respectively, and outside the power periphery, the firstand second pluralities of vias having adjacent vias, the adjacent viasbeing spaced apart by a via distance that is smaller than a quarterwavelength of the fundamental frequency, the first and secondpluralities of vias being connected by a via chain.
 3. The enclosure ofclaim 2 wherein the signals are on a signal plane located between thepower plane and the second ground plane.
 4. The enclosure of claim 1wherein N is an integer ranging from 1 to
 20. 5. The enclosure of claim1 wherein M is an integer ranging from 1 to
 20. 6. The enclosure ofclaim 1 wherein the first plurality of vias having electrical contact toa plurality of adjacent contacts, the adjacent contacts being spacedapart by a contact distance that is smaller than a quarter wavelength ofthe fundamental frequency.
 7. The enclosure of claim 6 wherein thecontacts are ones of controlled collapse chip connection (C4) bumps,ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pins.8. The enclosure of claim 1 further comprises a contact array to connectto at least the first ground plane and the power plane.
 9. The enclosureof claim 8 wherein the contact array is one of a C4 bump array, a BGAball array, and a FCPGA pin array.
 10. The enclosure of claim 9 whereinthe ground plane has a plurality of adjacent contacts, the adjacentcontacts being ones of controlled collapse chip connection (C4) bumps,ball grid array (BGA) balls, and flip chip pin grid array (FCPGA) pinsand spaced apart by a contact distance that is smaller than a quarterwavelength of the fundamental frequency.
 11. A packaged devicecomprising: a die containing an integrated circuit having signalsoperating at a fundamental frequency; a plurality of controlled collapsechip connection (C4) bumps attaching the die to a substrate; and anenclosure attaching to the die to reduce radiation, the enclosurecomprising: a power plane having a power surface and a power periphery,the power plane coupling power to the signals of the integrated circuit,and first and second ground planes having first and second groundsurfaces and first and second ground peripheries, the first and secondground planes coupling ground to the signals, the first and secondground planes being separated from the power plane by first and seconddistances, respectively, the first and second ground surfaces beinglarger than the power surface, the first and second ground peripheriesextending at least third and fourth distances from the power periphery,respectively, the third and fourth distances being N and M times largerthan the first and second distances, respectively.
 12. The packageddevice of claim 11 wherein the first and second ground planes have firstand second pluralities of vias located around the first and secondground peripheries, respectively, and outside the power periphery, thefirst and second pluralities of vias having adjacent vias, the adjacentvias being spaced apart by a via distance that is smaller than a quarterwavelength of the fundamental frequency, the first and secondpluralities of vias being connected by a via chain.
 13. The packageddevice of claim 12 wherein the signals are on a signal plane locatedbetween the power plane and the second ground plane.
 14. The packageddevice of claim 11 wherein N is an integer ranging from 1 to
 20. 15. Thepackaged device of claim 11 wherein M is an integer ranging from 1 to20.
 16. The packaged device of claim 11 wherein the first plurality ofvias having electrical contact to a plurality of adjacent contacts, theadjacent contacts being spaced apart by a contact distance that issmaller than a quarter wavelength of the fundamental frequency.
 17. Thepackaged device of claim 16 wherein the contacts are ones of controlledcollapse chip connection (C4) bumps, ball grid array (BGA) balls, andflip chip pin grid array (FCPGA) pins.
 18. The packaged device of claim11 wherein the enclosure further comprises a contact array to connect toat least the first ground plane and the power plane.
 19. The packageddevice of claim 18 wherein the contact array is one of a C4 bump array,a BGA ball array, and a FCPGA pin array.
 20. The packaged device ofclaim 19 wherein the ground plane has a plurality of adjacent contacts,the adjacent contacts being ones of controlled collapse chip connection(C4) bumps, ball grid array (BGA) balls, and flip chip pin grid array(FCPGA) pins and spaced apart by a contact distance that is smaller thana quarter wavelength of the fundamental frequency.
 21. A methodcomprising: coupling power to signals of an integrated circuit operatingat a fundamental frequency by a power plane having a power surface and apower periphery; and coupling ground to the signals by first and secondground planes having first and second ground surfaces and first andsecond ground peripheries, the first and second ground planes beingseparated from the power plane by first and second distances,respectively, the first and second ground surfaces being larger than thepower surface, the first and second ground peripheries extending atleast third and fourth distances from the power periphery, respectively,the third and fourth distances being N and M times larger than the firstand second distances, respectively.
 22. The method of claim 21 whereinthe first and second ground planes have first and second pluralities ofvias located around the first and second ground peripheries,respectively, and outside the power periphery, the first and secondpluralities of vias having adjacent vias, the adjacent vias being spacedapart by a via distance that is smaller than a quarter wavelength of thefundamental frequency, the first and second pluralities of vias beingconnected by a via chain.
 23. The method of claim 22 wherein the signalsare on a signal plane located between the power plane and the secondground plane.
 24. The method of claim 21 wherein N is an integer rangingfrom 1 to
 20. 25. The method of claim 21 wherein M is an integer rangingfrom 1 to
 20. 26. The method of claim 21 wherein the first plurality ofvias having electrical contact to a plurality of adjacent contacts, theadjacent contacts being spaced apart by a contact distance that issmaller than a quarter wavelength of the fundamental frequency.
 27. Themethod of claim 26 wherein the contacts are ones of controlled collapsechip connection (C4) bumps, ball grid array (BGA) balls, and flip chippin grid array (FCPGA) pins.
 28. The method of claim 21 furthercomprises connecting to at least the first ground plane and the powerplane by a contact array.
 29. The method of claim 28 wherein the contactarray is one of a C4 bump array, a BGA ball array, and a FCPGA pinarray.
 30. The method of claim 29 wherein the ground plane has aplurality of adjacent contacts, the adjacent contacts being ones ofcontrolled collapse chip connection (C4) bumps, ball grid array (BGA)balls, and flip chip pin grid array (FCPGA) pins and spaced apart by acontact distance that is smaller than a quarter wavelength of thefundamental frequency.